The present invention relates generally to buffer circuitry, and in particular the present invention relates to an integrated circuit low power/high speed buffer circuit.
Integrated circuits are often used to process externally provided analog or digital signals. A receiver circuit of the integrated circuit typically processes these signals. The receiver is coupled to an input connection and can receive data in a variety of different speeds. The receiver circuit can include input buffer circuits to receive the external signal. The buffer circuit can be a transistor that drives the data to internal circuitry. One type of integrated circuit receiver uses numerous sample-and-hold circuits to process high-speed analog data signals provided through a buffer circuit. For example, ten sample circuits are coupled to an input connection via a common buffer. The sample circuits are offset in phase, such that they each capture the input signal at a different time. The sample-and-hold circuitry can be viewed as a load capacitance being driven by the input buffer. As such, a greater sample-and-hold circuit population increases the load capacitance. Increasing the load capacitance results in a compromise between increased power and decreased operating speed.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a high-speed input circuit that reduces an effective input load capacitance.
The above-mentioned problems with integrated circuit input buffers and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an integrated circuit comprises input connections to receive first and second input signals, a plurality of buffer circuits coupled to the input connections, a plurality of sample circuits each coupled to one of the plurality of buffer circuits, and control circuitry coupled to the plurality of buffer circuits to selectively place some of the plurality of buffer circuits in a standby state.
In another embodiment an integrated circuit comprises differential input connections to receive first and second input signals, electrostatic discharge protection circuitry coupled to the differential input connections, and first and second buffer circuits coupled to the differential input connections. First and second sample circuits are respectively coupled to the first and second buffer circuits. Control circuitry coupled to the first and second buffer circuits selectively places either the first or second buffer circuit in a standby state.
Amethod of operating an integrated circuit input buffer circuit comprises receiving differential input signals on input connections, activating a first buffer circuit coupled to the input connections, and placing a second buffer circuit, coupled to the input connections, in a standby state. A current conducted by the second buffer circuit is less than a current conducted by the first buffer circuit.
Another method of operating an integrated circuit input buffer circuit comprises receiving differential input signals on input connections, coupling the differential input signals to a plurality of buffer circuits, and sequentially activating at least one of the plurality of buffer circuits. The remaining ones of the plurality of buffer circuits are placed in a standby state. A standby current conducted by the buffer circuits in the standby state is less than an operating current conducted by the activated buffer circuits.